A Methodology for Invasive Programming on Virtualizable Embedded MPSoC Architectures

AbstractExploiting the huge logic resources in current embedded devices has led to a plethora of on-chip multi-processor architec- tures. However, besides instantiating more and more soft-core processors on a chip, developing applications suited for such architectures still remains a hard task. A further step in the evolution of embedded multi-processing might be the so called Invasive Programming. In this paradigm, an application may be switched from sequential to parallel execution at runtime. A task may then dynamically invade currently unused processor resources in a multi-processor system to resume in parallel execution mode. This hardens existing problems, however, because not only the development of suited software, but also the creation of multi-processor architectures supporting this paradigm is needed. Therefore, this work presents a concise methodology to enable Invasive Programming properties on an embedded Multi-Processor System-on-Chip (MPSoC). This is achieved by combining a designer-guided code parallelization approach with a virtualizable, generic, and scalable embedded MPSoC architecture. To resolve data dependencies during task invasion, a processor-independent task-based communication scheme for the MPSoC is proposed. Moreover, a tool framework dedicated to the generic creation of virtualizable MPSoC is provided. The approach is demonstrated by the generation of an MPSoC featuring eight processors executing an application which dynamically switches at runtime between sequential and parallel execution

A novel technique for FPGA IP protection

The configuration data sequence of a field programmable gate array (FPGA) is an intellectual property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA hardware designs has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods need a cryptographic key to be stored in a non-volatile memory located on FPGA or in a battery-backed RAM (Random Access Memory) as done in some of the current FPGAs. The expenses with the proposed methods are, occupation of larger area on FPGA in the former case and limited lifetime of the device in the latter. In contrast, we propose a novel method which combines the dynamic partial reconfiguration (dynamic PR) feature of an SRAM-based FPGA with the public key cryptography (PKC) to protect the FPGA configuration files without the need to store any keys on FPGA